Memory cells of dynamic random access memories (DRAMs) based on a 1T1C cell concept each comprise a storage capacitor for storing an electric charge, which characterizes a data content of the memory cell and a select transistor for addressing the storage capacitor. In trench capacitor designs, the storage capacitor is formed within a semiconductor substrate beneath a substrate surface. The select transistors are arranged oriented substantially next to one another at or on a substrate surface of the semiconductor substrate and are at least in part formed beneath the substrate surface. In each case, one select transistor is electrically conductively connected to one of the electrodes of the storage capacitor assigned to the select transistor.
A conventional method for fabricating a storage capacitor using the trench capacitor concept and a storage capacitor fabricated using the method are shown in simplified form in FIGS. 1 to 4. According to these figures, a protective layer 3, which is composed of a lower partial protective layer 32 and an upper partial protective layer 31, is applied to a substrate surface 10 of a semiconductor substrate 1, for example, made from monocrystalline, weakly p-doped silicon. The lower partial protective layer 32 is an oxide layer (pad oxide), while the upper partial protective layer 31 is a silicon nitride layer (pad nitride). The upper partial protective layer 31 protects sections of the semiconductor substrate 1, which it covers during subsequent process steps. The lower partial protective layer 32 assists with subsequent removal of the upper partial protective layer 31.
To form the storage capacitors 9, a hole mask is produced over the protective layer 3 by a lithographic method. Hole trenches 2 are introduced into the semiconductor substrate 1 through the protective layer 3 with the aid of the hole mask. A maximum aspect ratio of a minimum width to the depth of the hole trenches 2 is predetermined by the manufacturing technology used and is typically approximately 1:50. The hole mask is removed. Outer electrodes 11 are formed in an electrode section 14 of the semiconductor substrate 1 surrounding lower sections of the hole trenches 2, for example, by outdiffusion from a temporary filling of the hole trenches 2 with n-doped material. The hole trenches 2 are lined with a capacitor dielectric 5. After a first polysilicon filling has been introduced into the hole trenches 2, the polysilicon filling and the capacitor dielectric 5 are shaped back to below a top edge of the electrode section 14. A first filling section 16 of the inner electrode 6 to be formed originates from the polysilicon filling. Above a top edge of the first filling section 61, the hole trench 2 is lined with an insulation collar 4.
FIG. 1 shows two hole trenches 2 following the formation of the insulation collars 4. The protective layer 3 formed from the pad oxide 32 and the pad nitride 31 rests on the substrate surface 10 of the weakly p-doped semiconductor substrate 1. The hole trenches 2 extend through the protective layer 3 into the semiconductor substrate 1. In the electrode section 14 of the semiconductor substrate 1, the outer electrodes 11 are formed as n-doped regions, which each surround the lower section of the hole trenches 2. In each case, a first filling section 61 of the inner electrode 6 to be formed is provided inside the hole trenches 2 in the lower section. The first filling section 61 is separated from the outer electrode 11 or from the semiconductor substrate 1 by the capacitor dielectric 5. Above the first filling section 61, the hole trenches 2 are each lined by the insulation collar 4, which consists, for example, of silicon oxide produced from tetraethylorthosilane (TEOS oxide).
A second polysilicon filling is introduced into the hole trenches 2 and etched back to below the substrate surface 10. The etched-back polysilicon forms a second filling section 62 of the inner electrode 6 which is to be formed.
FIG. 2 shows the second filling section 62, which in each case adjoins the first filling section 61 in the interior of the hole trench 2. Sections of the insulation collar 4 located above the second filling section 62 are removed. A top edge of the insulation collar 4 determines a bottom edge of a transition surface 7, which is subsequently to be formed (buried strap interface).
FIG. 3 shows the insulation collars 4 once the insulation collars 4 have been shaped back. These collars are in an insulation section 16 of the semiconductor substrate 1 and insulate the second filling section 62 of the inner electrodes to be formed from the surrounding semiconductor substrate 1 and from doped regions and diffusion zones that are subsequently formed in the semiconductor substrate 1.
A third polysilicon filling is introduced into the hole trenches 2 and shaped back to below the substrate surface 10. In the process, the third polysilicon filling forms a third filling section 63 of the inner electrode 6 to be formed. Before the third polysilicon filling is introduced, a section of the semiconductor substrate 1 that is uncovered at a trench wall of the hole trench is optionally subject to a nitriding treatment in order to optimize the properties of the transition surface 7 to be formed.
FIG. 4 illustrates the third filling section 63 adjoining the second filling section 62. The height of the third filling section 63 defines a top edge of the transition surface 7. The semiconductor substrate 1 is surface-nitrided in the region of the transition surface 7 and has a nitrided layer 71. The transition surface 7 provides an electrically conductive connection between the inner electrode 6, formed from the first, second and third filling sections 61, 62, 63, of the storage capacitor 9 and a connection structure 91 formed in a connection section 15 of the semiconductor substrate 1. The connection structure 91 is, for example, a first source/drain region (S/D junction) of a select transistor assigned to the storage capacitor 9 or a doped connection region formed by outdiffusion through the transition surface 7. The insulation collar 4 and the transition surface 7 are each provided in the hole trench 2 beneath the substrate surface 10.
It is generally desired for the horizontal dimensions of memory cells having a storage capacitor to be reduced without any detrimental effect on the charge storage capacitance of the storage capacitor, or alternatively, for given horizontal dimensions to improve the charge storage options on the storage capacitor and increase the capacitance of the storage capacitor.
For example, to increase the capacitance, it is known to increase the electrode surface area by the hole trenches below a level of the select transistors being widened in a bottle shape by a wet bottle etching process or by hemispherical structures being applied to the wall of the hole trenches (hemispherical silicon grain deposition). Furthermore, it is known to increase the capacitance of the storage capacitors by selecting a material of high permittivity (high k dielectric), for example, aluminum oxide or hafnium oxide.
A method for fabricating a hole trench storage capacitor for a DRAM memory cell, which allows the hole trench storage capacitor to be formed with a higher capacitance, is desirable. A hole trench storage capacitor with a high capacitance is also desirable. Furthermore improved fabrication of the single-sided buried strap connection (SSBS) of the storage trench or hole trench storage capacitor to the associated select transistor is desirable.